A chip may embody one of a General Purpose Computer (“GPC”), an Application Specific Integrated Circuit (“ASIC”), or a Field Programmab1e Gate Array (“FPGA”), or a combination thereof. A GPC has fixed logic and uses software instructions to process data. An ASIC has fixed logic and processes data through functions built from hardwired gates. An FPGA has reconfigurable logic and processes data through functions built from configurable gates. In general, among the GPC, the ASIC, and the FPGA, the GPC provides the most flexibility. As a result, the GPC can be applied in the widest variety of applications. The ASIC has the best performance for specific applications but a much narrower range of applications in which it can he employed. The FPGA has good performance for specific applications and can be adapted for a variety of applications up until the time that it is deployed. More recently, FPGAs have been employed where the whole or part of the FPGA is reconfigured after the FPGA has been deployed to suit a specific application. Current designs are ineffective because, for example, they result in communication bottlenecks. Further, all of the above approaches result in inefficiencies because most logic gates on the chip are idle for significant portions of time, i.e., many logic gates have limited utility over the entire time that the chip is operating. In addition, current designs do not accommodate runtime-processing adaptation with high efficiency, i.e., these approaches do not provide high utilization of the gates on the FPGA.
Still more recent designs provide chips that are reconfigurable while being employed in an operating circuit, and go by other names (e.g., runtime reconfigurable, dynamically reconfigurable, etc.) than “FPGA.” however, provided that the chip is made of gates and its functions can be reconfigured, these chips are still considered a “FPGA.”